The present invention relates to analog-to-digital converters, and, more particularly, to an analog-to-digital converter having precise differential voltage double interpolation using non-linear floating semiconductor resistors.
Analog-to-digital converters (ADCs) are circuits used to convert signals from the analog domain, where the signals are represented by continuous quantities such as voltage and current, to the digital domain. These circuits can be implemented in a large number of ways. Established A/D conversion techniques include flash, sigma-delta, sub-ranging, successive approximation, and integrating.
A conventional flash type A/D converter is one of the fastest structure which directly utilizes 2nxe2x88x921 comparators to compare the input analog voltage with 2nxe2x88x921 reference voltages and then generate n bits output digital code, where n is the number of bit resolution. The disadvantage of this structure is its large number of comparators needed, thus increasing power consumption and chip area.
An improved flash type A/D converter uses numerous interpolation circuits to reduce the number of comparators. These circuits interpolate the output voltage by means of a number of series-connected impedance elements.
This precise differential voltage interpolation between two known differential voltages has been widely used in mixed signal/analog circuit design, especially in low power circuits where known differential voltages are generated using two amplifiers having high power consumption, and where an intermediate voltage is generated by interpolation to eliminate the power consumption of one amplifier. The demand for low power consumption in portable devices (i.e. cellular phones, PDAs, and digital still cameras) forecasts that precision differential interpolation will be implemented in more designs.
Specifically, the conventional four-input interpolation scheme includes for every pair of amplifiers or buffers, five comparators to set five decision levels. Each amplifier has a differential input and a differential output. Connected to each differential output leg between the two amplifiers is a series of two silicide-blocked resistors. A node between the two resistors defines the intermediate voltage between the voltage level at the first and the second amplifier for each differential output leg. Each of the differential output legs along with the intermediate voltage nodes between each resistor pair define a set of five decision levels. These levels are used to directly translate the analog input voltage level into a digital one.
In an effort to achieve good linearity, interpolation resistors need to be precise and cannot have terminal voltage dependency beyond a certain level. Silicide-blocked resistors meet these requirements, however, they require large area and extra processing steps; thereby increasing the cost of the ADC.
Thus, there exists a need for an inexpensive analog-to-digital converter having a precise differential voltage interpolation that does not implement the use of silicide blocked resistors.
To address the above-discussed deficiencies of flash analog-to-digital converters (ADC), the present invention teaches an inexpensive ADC having precise differential voltage interpolation without the use of silicide-blocked resistors. The ADC in accordance with the present invention includes a reference conversion voltage output portion for converting an analog input voltage on the basis of a plurality of reference voltages into a plurality of reference conversion voltages. An intermediate voltage generating portion includes a predetermined number of non-linear resistance units respectively provided between one voltage and the other voltage in pairs of a predetermined number of the plurality of reference conversion voltages to generate a plurality of intermediate voltages by resistance division using the predetermined number of non-linear resistance units. A voltage interpolator connects to the intermediate voltage generating portion to generate a plurality of conversion voltages. A digital data output portion couples to receive the plurality of conversion voltages to provide the digital output voltage using double interpolation. Each of the predetermined number of non-linear resistance units includes a first input terminal connected to the one voltage, a second input terminal connected to the other voltage, and a plurality of non-linear resistor elements having the same resistance value connected in series between the first and second input terminals. The plurality of intermediate voltages includes at least part of voltages obtained from one end of each of the plurality of non-linear resistor elements.
The invention solves the insufficiencies of the prior art by using a double interpolation scheme and input common mode voltage adjustment technique, where precise differential voltage interpolation is achieved by using inexpensive, small semiconductor resistor either n-well or MOS resistors.
Advantages of this design include but are not limited to a inexpensive ADC having precise differential voltage interpolation such that silicon area and cost are reduced a 5% cost reduction in current standard CMOS technology which translates to a greater than 5% profit margin.